1. Technical Field
The present invention relates to a transistor and a method for manufacturing thereof, and in particular relates to a vertical metal oxide semiconductor field effect transistor (vertical MOSFET) and a method for manufacturing thereof.
2. Related Art
A typical conventional technology for a vertical MOSFET includes a configuration described in Japanese Patent Laid-Open No. H05-335582 (1993). FIG. 6 is a diagram, showing a transistor of a related art having a cross-sectional configuration similar to that of a MOSFET disclosed in Japanese Patent Laid-Open No. H05-335582. In FIG. 7, a plan view of the transistor of the related art that is manufactured using a similar process disclosed in Japanese Patent Laid-Open No. H05-335582 is shown. FIG. 6 is a cross-sectional view along line A-A′ of FIG. 7.
A transistor shown in FIG. 6 and FIG. 7 is manufactured by the following procedure. FIGS. 8A and 8B, FIGS. 9A and 9B and FIG. 10 are cross-sectional views, showing a process for manufacturing the transistor shown in FIG. 6 and FIG. 7.
First of all, as shown in FIG. 8A, a gate trench 202 is formed in a semiconductor substrate 201. More specifically, the formation of the gate trench is carried out via a selective etching process utilizing a photolithographic technology. Next, a gate oxide film 203 is formed on the entire surface thereof via a thermal oxidation process. Subsequently, a polysilicon film 204 for forming a gate electrode is formed via a chemical vapor deposition (CVD) on the entire surface thereof (FIG. 8B). Then, an etching process is conducted for such polysilicon film 204, so that the polysilicon film 204 partially remains in the gate trench 202 (FIG. 9A).
Subsequently, a p-type base region 205 for active cell is formed via an ion implantation with boron and a thermal processing, and a mask having openings that serve as regions for forming p+ type base regions 209 is formed via a patterning process of a photolithographic technology, and then an ion implantation of borondifluoride (BF2) and a thermal processing are conducted through the openings to selectively form the P+ type base regions 209 in a predetermined locations. Next, a mask having openings that serve as regions for forming n+ type source regions 206 is formed via a patterning process of a photolithographic technology, and then an ion implantation of arsenic and a thermal processing are conducted through the openings to selectively form the n+ type source regions 206 in predetermined locations (FIG. 9B).
Next, a boro-phospho silicate glass (BPSG) film is formed via a CVD process to form an interlayer insulating film 207, and then predetermined locations of the BPSG are selectively removed via a photolithographic technology and an etching process (FIG. 10). Next, a barrier metal film 210 is formed on the surface thereof via a sputter process, and subsequently, a sputter process of aluminum is conducted to form a source electrode 212. The MOSFET shown in FIG. 6 is thus obtained by the above-mentioned procedure.
However, the present inventors discovered that there are needs to be improved in the vertical MOSFET of the related art in view of the following aspects. A specific description of the above-described needs will be described in reference to the above-described constitutions shown in FIG. 6.
In the device shown in FIG. 6, since the source regions are formed by employing a mask in the manufacturing process (FIG. 10), as shown in FIG. 11, misalignment of the patterned mask may cause a decreased area of a source contact. Thus, this could increase the source contact resistance.
In the structure including the contact of the source contact in the cell unit of the MOS transistor with the source electrode as described above as a two-dimensional pattern obtained by forming the source region by using a mask, a reduced dimensional area of the source contact due to misalignment of the patterned mask may cause an increased source contact resistance. An increased source contact resistance causes an increased on-resistance of the MOS transistor, leading to decreased properties thereof. Thus, it is required that the source electrode is electrically coupled to source region in a stable condition.